A PID controller based on the processor utilization artifact within a real-time multitask control system

Abstract

Codesign of control and scheduling systems is commonly used in the literature to address scheduling artifacts such as latencies and jitters. However, As controllers’ designs remain unchanged and fail to express any concerns regarding this matter, it becomes challenging to quantify the quality of control and its trade-off with resource utilization while adapting control or scheduling settings at runtime. In the present article, we propose a new proportional–integral–derivative (PID) controller design for the problem of scheduling artifacts. Based on our prior work, the latency processor utilization is revealed as a hidden artifact for the control deterioration when developing new predicted PID controller terms. This artifact effect is proven analytically using a codesign task model and considering an extrapolated measurement. The effectiveness of the proposed solution is assessed with a benchmark system and compared with previous works.