Design and Implementation of an Area and Power-efficient Reconfigurable Hearing Aid using Interpolated Sub-band Distribution Technique

Abstract

A hearing aid is a compensatory device that helps in overcoming various hearing disabilities. Since different people possess different hearing problems and the requirement gets changed over time, it is necessary to design a reconfigurable hearing aid which is generic in nature such that it supports various hearing disabilities without modifying the hardware components. The objective of the paper is to implement a reconfigurable digital hearing aid which is hardware efficient and it is auto-adaptable to disabilities ranging from mild to severe intensities. Since multipliers and LUTs are power hungry elements, we have proposed a design which is multiplier less and LUT-less DA Architecture. The prototype filter is a FIR filter which is designed using LUT-less Distributed Arithmetic Algorithm that saves 64% of logic elements & memory and 76% of power utilization. As it is a multiplier-less as well as LUT- less architecture, hence this can be claimed to be area and power efficient design. The delays and matching errors are within the standard limits which are accepted globally. The input audio spectrum is divided into three regions and for each region there are four different filter banks are proposed using interpolated sub-bands distribution. Xilinx System Generator is used to implement the proposed design. The proposed design requires least manual configuration for selection of filter banks for audiogram matching which also minimizes the trial-anderror method to establish the best match with the person’s audiogram.