Hardware in the Loop-Based Testing of Three Schemes for Mitigation the Effect of Unsymmetrical Grid Faults on DFIG

Abstract

This paper presents three-proposed schemes to mitigate the effect of unsymmetrical voltage sag fault on a wind-driven grid-connected Double Fed Induction Generator (DFIG). The first tested scheme comprises a static compensator (STATCOM) connected to the DFIG stator, while a three-phase parallel RL external impedance is connected to the rotor circuit in the second scheme. The STATCOM and the added rotor impedance are connected simultaneously in the third scheme. The effect of applying the three schemes on the responses of the stator and rotor voltages and currents, the dc-link voltage and current, the electrical torque, and the rotor speed during an unsymmetrical voltage sag are presented and compared at sub-and super-synchronous speeds. All systems were emulated, implemented, and tested through an OPAL RT-4510 Digital Real-Time Simulator (DRTS) in a Hardware-In-the-Loop (HIL) application. The internal Field-Programmable Gate Array (FPGA) chip assisted in using this platform as a Rapid Control Prototyping (RCP) for virtual mitigation control and testing. The Matlab/ Simulink RT-lab software packages combination helped in the RT development environment. All real-time waveforms of parameters for the proposed scenarios were monitored through the HIL-controller and data acquisition interface and then compared with the simulated results. The results reveal that the simulation waveforms and the real time waveforms are congruent. Results prove the better performance of the DFIG during unsymmetrical voltage sag for sub-synchronous speed when applying both protection schemes, while best results are obtained when using only the rotor impedance at super-synchronous speed operation of the DFIG.