Parallel Implementation of Nios Ii Multiprocessors, Cepstral Coefficients of Mel Frequency and MLP Architecture in Fpga: the Application of Speech Recognition

Author:

Eddine Khamlich Salah1,Fathallah Khamlich2,Atouf Issam2,Mohamed Benrabh2

Affiliation:

1. National School of Applied Sciences, Research teams “SEIA” LaSTI, Sultan Moulay Slimane University, KHOURIBGA, Morocco

2. LTI Lab. Faculty of Sciences Ben M’sik Hassan II University, Casablanca- Morocco

Abstract

Speech processing in real time requires the use of fast, reconfigurable electronic circuits capable of handling large amounts of information generated by the audio source. This article presents hardware implementations of a multilayer perceptron (MLP) and the MFCC algorithm for speech recognition. These algorithms have been implemented in hardware and tested in an on-board electronic card based on a reconfigurable circuit (FPGA). We also present a comparative study between several architectures of MLP and with the literature on the level of costs with regard to the surface of silicon, the speed and the computing resources required. Following the FPGA circuit modification, we created NIOSII processors to physically implement the architecture of ANN-type MLPs and MFCC speech recognition algorithms and perform real-time speech recognition functions.

Publisher

World Scientific and Engineering Academy and Society (WSEAS)

Subject

Computer Networks and Communications,Computer Vision and Pattern Recognition,Signal Processing,Software

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