Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures

Abstract

Reliability is a major concern in the microprocessor industry. In terms of power consumption, SRAM plays a key role in improving processing performance. Improving SRAM efficiency requires changes to the array structure. A general method in which the SRAM array has more rows than columns.The above techniques are proposed to improve efficiency by 10% for 8kbit and 40% for 64kbit at the same SRAM byte density and supply voltage. Implement suggested deep submicron technology for better reliability. Many proposed designs focus on low power consumption, often with reduced response times.As the technology scales, the power consumption of on-chain system devices with gate leakage, subthreshold current, and tunneling increases significantly. Small SRAM capabilities are important.This task demonstrates the potential of using larger SRAM array structures to achieve better SRAM energy efficiency, especially when the number of rows is less than the number of low-power columns. Compared to traditional 8T SRAM, the proposed 10T cell uses less power, has a different temperature and better performance.