Affiliation:
1. Delft University of Technology, 2629 HS Delft, The Netherlands
2. European Space Agency, 2200 AG Noordwijk, The Netherlands
Abstract
This paper describes the work carried out to extend the NOEL-V platform to include data-level parallelism (DLP) by implementing an integer subset of the RISC-V Vector Extension. The performance and resource utilization efficiency of the resulting vector processor for different levels of DLP (i.e., number of lanes) have been compared to the baseline scalar processor on a Xilinx Kintex Ultrascale field-programmable gate array, employing typical kernels for compute-intensive applications. The role of the memory subsystem has also been investigated, comparing the results obtained with a low-latency and a high-latency main memory. The results show that the speed-up due to the use of the vector pipeline increases with the number of lanes in the vector processor, achieving up to 23.0× the performance of the scalar processor with only 4.3× the resources of the baseline scalar processor. Using an implementation with 32 lanes increases performance even for problem sizes larger than the number of lanes, achieving up to more than 11.7× the performance of the scalar processor with just 1.9× its resource utilization for [Formula: see text] matrix multiplications. This work proves that implementations of the selected subset are easily scalable and fit for small-processor implementations in highly constrained space embedded systems.
Publisher
American Institute of Aeronautics and Astronautics (AIAA)
Subject
Electrical and Electronic Engineering,Computer Science Applications,Aerospace Engineering
Cited by
1 articles.
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1. Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03