Surrogate-Based Modeling Techniques for Mapping Transistor Figures of Merit onto Compact Model Parameters-Reference-Cited by-同舟云学术

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Surrogate-Based Modeling Techniques for Mapping Transistor Figures of Merit onto Compact Model Parameters

Published:2022-10-09 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Integrated Reliability Workshop (IIRW)
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Author:

Velarde Gonzalez Fabio A.¹,Chavez-Hurtado Jose L.²,Lange Andre¹,Mikolajick Thomas³

Affiliation:

1. Fraunhofer Institute for Integrated Circuits IIS Division Engineering of Adaptive Systems EAS,Dresden,Germany

2. ITESO University,Dep. of Electronics, Systems, and Informatics,Tlaquepaque,México

3. IHM Technische Universität Dresden,Dresden,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10032732/10032733/10032755.pdf?arnumber=10032755

Reference15 articles.

1. A Tutorial on Latin Hypercube Design of Experiments

2. Predictive technology model - 22nm ptm lp model;integration,2008

3. Procedure for measuring nchannelmosfet hot carrier-induced degradation under dc stress;jedec,2001

4. Challenges and solution approaches for simulation-based reliability assessment – degradation modeling

5. Kriging Metamodeling in Discrete-Event Simulation: An Overview

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