Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation
Author:
Affiliation:
1. STMicroelectronics,Rousset,France
2. Aix-Marseille University,CNRS, IM2NP UMR,Marseille,France,7334
3. University of Côte d'Azur,Polytech’Lab UPR UCA,Sophia-Antipolis,France,7498
4. STMicroelectronics,Crolles,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10032732/10032733/10032763.pdf?arnumber=10032763
Reference19 articles.
1. Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology
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3. A unified mobility model for device simulation—I. Model equations and concentration dependence
4. Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology
5. Model for the electric fields in LDD MOSFETs. I. Field peaks on the source side
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