Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

Author:

Zhang L.1,Kraatz M.1,Aubel O.2,Hennesthal C.2,Im J.1,Zschech E.3,Ho P. S.1

Affiliation:

1. Laboratory for Interconnect and Packaging, Microelectronics Research Center, The University of Texas at Austin, PRC/MER, Mail Code: R8650, Austin, TX 78712

2. Globalfoundries Dresden Module One LLC & Co. KG, 01109, Dresden, Germany

3. Fraunhofer Institute for Non-Destructive Testing IZFP, Dresden, Germany

Publisher

IEEE

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

2. Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

3. Mechanical Robustness of Patterned Structures and Failure Mechanisms;More-than-Moore Devices and Integration for Semiconductors;2023

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