3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Author:

Park Jong BeomORCID,Davis William Rhett,Franzon Paul D.

Funder

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-09

2. Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor;Proceedings of the 2022 International Symposium on Memory Systems;2022-10-03

3. Design for 3D Stacked Circuits;2021 IEEE International Electron Devices Meeting (IEDM);2021-12-11

4. A Virtual Platform for Object Detection Systems;2021 IEEE International 3D Systems Integration Conference (3DIC);2021-10

5. Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching;2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA);2021-06

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