A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time <formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex> </formula> ADC for a Digital Closed-Loop Class-D Amplifier-Reference-Cited by-同舟云学术

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A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time $\Sigma\Delta$ ADC for a Digital Closed-Loop Class-D Amplifier

Published:2015-03 Issue:3 Volume:62 Page:645-653
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Donida Achille,Cellier Remy,Nagari Angelo,Malcovati Piero,Baschirotto Andrea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7047256/06998054.pdf?arnumber=6998054

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of an Optimized 120-dB Dynamic Range Current-Steering DAC for Class-D Audio Amplifier;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

2. A Mixed Analog-Digital Class-D Amplifier with Third-Order Loop Filter for Audio Applications;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-03

4. Design and Analysis of Higher-Order Sigma Delta Modulator;Advances in Intelligent Systems and Computing;2020

5. A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter;IEEE Journal of Solid-State Circuits;2017-12

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