A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme
Author:
Funder
University of Tokyo
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8667917/08584417.pdf?arnumber=8584417
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements;IEEE Access;2022
2. A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-12
3. A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC);2021-09-13
4. An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05
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