An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

Author:

Wang Yu-Shun,Hsieh Min-Han,Li James Chien-Mo,Chen Charlie Chung-Ping

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-07

2. Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” [Dec 07 2696-2705];IEEE Transactions on Circuits and Systems I: Regular Papers;2014-07

3. Low Voltage and Low Power 64-Bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure;2014 International Symposium on Computer, Consumer and Control;2014-06

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