Gate Stack Resistance and Limits to CMOS Logic Performance

Author:

Wachnik Richard A.,Lee Sungjae,Pan Li-Hong,Li Hongmei,Lu Ning,Wang Jing,Bernicot Christophe,Bingert Raphael,Randall Mai,Springer Scott K.,Putnam Christopher S.

Funder

independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics, Div. Semiconductor Research & Development Center, Hopewell Junction, NY

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Case Studies in the Evaluation of Novel Transistors;RF and Time-domain Techniques for Evaluating Novel Semiconductor Transistors;2021-12-16

2. AC Device Variability in High- $\kappa$ Metal-Gate CMOS Technology;IEEE Electron Device Letters;2019-01

3. Extraction of Drain Current Thermal Noise in a 28 nm High- ${k}$ /Metal Gate RF CMOS Technology;IEEE Transactions on Electron Devices;2018-06

4. Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter;IEEE Transactions on Electron Devices;2016-07

5. Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS;IEEE Electron Device Letters;2016-02

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