Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )-Reference-Cited by-同舟云学术

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Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )

Published:2017-11 Issue:11 Volume:64 Page:2894-2906
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ibrahim Atef^ORCID,Gebali Fayez

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/8082393/07926316.pdf?arnumber=7926316

Cited by 30 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Low-complexity systolic array structure for field multiplication in resource-constrained IoT nodes;Ain Shams Engineering Journal;2023-10

3. Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF(2m);2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01

4. Squeezing Area of the Versatile GF (2^m) GNB Arithmetic Operators;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-06

5. Word-Based Processor Structure for Montgomery Modular Multiplier Suitable for Compact IoT Edge Devices;Mathematics;2023-01-08

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