Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for $GF(2^{m})$ Based on Irreducible All-One Polynomials-Reference-Cited by-同舟云学术

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Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for $GF(2^{m})$ Based on Irreducible All-One Polynomials

Published:2017-02 Issue:2 Volume:64 Page:399-408
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Meher Pramod Kumar,Lou Xin

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7835743/07605554.pdf?arnumber=7605554

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power Efficient Implementation of ECC Using LCSLA Based Dual Field Vedic Multiplier;Proceedings of the Bulgarian Academy of Sciences;2023-12-21

2. Word-Based Processor Structure for Montgomery Modular Multiplier Suitable for Compact IoT Edge Devices;Mathematics;2023-01-08

3. Low-Complexity One-Dimensional Parallel Semi-Systolic Structure for Field Montgomery Multiplication Algorithm Perfect for Small IoT Edge Nodes;Mathematics;2022-12-26

4. Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices;Alexandria Engineering Journal;2022-12

5. A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-12

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