Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
Author:
Affiliation:
1. Duke University,Department of Electrical and Computer Engineering
2. NVIDIA Corporation
3. School of Electrical, Computer and Energy Engineering, Arizona State University
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10350036/10350038/10351068.pdf?arnumber=10351068
Reference27 articles.
1. 3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS
2. Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
3. A novel scheme to reduce power supply noise for high-quality at-speed scan testing
4. Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs
5. Enhancing Delay Fault Coverage through Low Power Segmented Scan
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