Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8790390/8809485/08809534.pdf?arnumber=8809534
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08
2. Position error-free control of magnetic domain-wall devices via spin-orbit torque modulation;Nature Communications;2023-11-23
3. DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories;IEEE Transactions on Computers;2023-09-01
4. ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees;IEEE Transactions on Computers;2023-05-01
5. Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT;IEEE Transactions on Computers;2023-04-01
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