Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Author:

Miryala Sandeep,Kaur Baljit,Anand Bulusu,Manhas Sanjeev

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. ANN-based Standard Cell Switching Waveforms Characterization Model for PVT Variations;2024 4th International Conference on Neural Networks, Information and Communication (NNICE);2024-01-19

2. Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

3. Complete Timing Model of ECSM Lookup Table for CMOS Inverter;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

4. Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

5. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility;Journal of Zhejiang University SCIENCE C;2012-06

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