Automatic die placement and flexible I/O assignment in 2.5D IC design
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7080985/7085355/07085480.pdf?arnumber=7085480
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09
2. Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-11
3. MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems;2019 22nd Euromicro Conference on Digital System Design (DSD);2019-08
4. Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration;IPSJ Transactions on System LSI Design Methodology;2017
5. Modular Placement for Interposer based Multi-FPGA Systems;Proceedings of the 26th edition on Great Lakes Symposium on VLSI;2016-05-18
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