Simultaneous buffer and interlayer via planning for 3D floorplanning
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4804412/4810250/04810385.pdf?arnumber=4810385
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
2. Fast Buffer Count Estimation in 3D IC Floorplanning;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-01
3. Thermal and Wirelength Optimization With TSV Assignment for 3-D-IC;IEEE Transactions on Electron Devices;2019-01
4. Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
5. Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-08
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