A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/7336577/07244336.pdf?arnumber=7244336
Cited by 53 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 70dB SNDR 20MHz-BW VCO-Based CT Sturdy MASH Delta-Sigma Modulator with Robust Quantization Error Extraction;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling;IEEE Journal of Solid-State Circuits;2024
3. Mixed-Order Correlated Dual-Loop Sturdy MASH CT-$\Delta \Sigma $ Modulator With Distributed Signal Feed-In and VCO Quantizer;IEEE Journal of Solid-State Circuits;2024
4. Oversampling ADC: A Review of Recent Design Trends;IEEE Access;2024
5. A Lean Noise-Cancelling Sturdy MASH Delta-Sigma ADC with a Noise-Shaping SAR Stage;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
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