A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS

Author:

Malki Badr,Verbruggen Bob,Martens Ewout,Wambacq Piet,Craninckx Jan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 12-bit 75 MS/s Asynchronous SAR ADC with Gain-Boosting Dynamic Comparator;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023

3. A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-02

4. A Type-II Phase-Tracking Receiver;IEEE Journal of Solid-State Circuits;2021-02

5. An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-11

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