A 0.4 V 63 $\mu$W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/7279217/07254248.pdf?arnumber=7254248
Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06
2. A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A 23.7‐uW 93.5‐dB SNDR delta‐sigma modulator for healthcare and medical diagnostics;Electronics Letters;2024-03
4. 103.1-dB DR Switched-Resistor Delta-Sigma Modulator With Chopped Negative-R for Suppressing Low-Bandwidth Noise;IEEE Access;2023
5. Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier;IEEE Journal of Solid-State Circuits;2022-11
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