A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique-Reference-Cited by-同舟云学术

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A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

Published:2013-07 Issue:7 Volume:48 Page:1721-1729
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Hyung Seok,Ornelas Carlos,Chandrashekar Kailash,Shi Dan,Su Pin-en,Madoglio P.,Li W.Y.,Ravi A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6545290/06494316.pdf?arnumber=6494316

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2. DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW;Jurnal Teknologi;2019-12-04

3. A new method for improving sampling bandwidth of power analyzer;2019 14th IEEE International Conference on Electronic Measurement & Instruments (ICEMI);2019-11

4. Introduction;Analog Circuits and Signal Processing;2019

5. A 0.5-bit step multi-resolution adjustable-input range reconfigurable noise-shaping TDC using multi-step quantizer gated-ring oscillators;Analog Integrated Circuits and Signal Processing;2018-02-19

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