A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC-Reference-Cited by-同舟云学术

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A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC

Published:2012-06 Issue:6 Volume:47 Page:1334-1343
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tseng Chien-Jian,Chen Hung-Wei,Shen Wei-Ting,Cheng Wei-Chih,Chen Hsin-Shu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6203507/06188519.pdf?arnumber=6188519

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 12-bit 350-MS/s Pipelined ADC in 40-nm CMOS;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22

2. Pipeline Analog-to-Digital Conversion;Analog-to-Digital Conversion;2021-10-22

3. A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier;Microelectronics International;2020-09-11

4. DESIGN OF HIGH-RESOLUTION (12-14 BIT) MULTI-CHIP CONVEYOR ADCS WITH 0.5-1 GHZ CONVERSION FREQUENCY;Modeling of systems and processes;2019-10-24

5. A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs;Journal of Circuits, Systems and Computers;2019-02-24

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