Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor-Reference-Cited by-同舟云学术

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Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Published:2013-01 Issue:1 Volume:48 Page:140-149
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sathe Visvesh S.,Arekapudi Srikanth,Ishii Alexander,Ouyang Charles,Papaefthymiou Marios C.,Naffziger Samuel

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6399535/06332544.pdf?arnumber=6332544

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A resonant metamaterial clock distribution network for superconducting logic;Nature Electronics;2022-03-24

2. A 1.25-GHz Fully Integrated DC–DC Converter Using Electromagnetically Coupled Class-D LC Oscillators;IEEE Journal of Solid-State Circuits;2021-12

3. Resonant Energy Recycling SRAM Architecture;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-04

4. 0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-01

5. A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoC;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-11

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