A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding-Reference-Cited by-同舟云学术

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A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Published:2015-04 Issue:4 Volume:50 Page:1070-1079
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Knag Phil,Kim Jung Kuk,Chen Thomas,Zhang Zhengya

Funder

Defense Advanced Research Projects Agency (DARPA) under Cooperative Agreement HR0011-13-2-0015

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7066864/07015626.pdf?arnumber=7015626

Cited by 58 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm;IEEE Journal of Solid-State Circuits;2024

2. A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses;IEEE Journal of Solid-State Circuits;2024

3. A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

4. A 5.37-TSOPS/W Reconfigurable Neuron Array with Dual-mode Neurons and Asynchronous Synapses for Energy-Efficient Inference and Biological Neural Network Simulation;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

5. Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence;Proceedings of the IEEE;2023-06

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