An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI-Reference-Cited by-同舟云学术

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An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 $\times$ 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI

Published:2019-02 Issue:2 Volume:54 Page:560-568
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Taco Ramiro^ORCID,Levi Itamar,Lanuzza Marco^ORCID,Fish Alexander

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8629373/08574058.pdf?arnumber=8574058

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3. Exploiting Dual Mode Logic for Approximate Computing;2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM);2023-10-10

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5. FlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic;IEEE Solid-State Circuits Letters;2023

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