A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics-Reference-Cited by-同舟云学术

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A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

Published:2015-11 Issue:11 Volume:50 Page:2533-2548
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tsai Jen-Huan,Ko Sheng-An,Wang Chia-Wei,Yen Yang-Chi,Wang Hui-Huan,Huang Po-Chiun,Lan Po-Hsiang,Shen Meng-Hung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7307914/07274369.pdf?arnumber=7274369

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