Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors-Reference-Cited by-同舟云学术

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Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors

Published:2022-07-01 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Region 10 Symposium (TENSYMP)
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Author:

Pathak Ketki C.¹,Darji Anand D.²,Sarvaiya Jignesh N.²

Affiliation:

1. Sarvajanik College of Engineering & Technology,Electronics & Communication Engineering,Surat,Gujarat,India

2. Sardar Vallabhbhai National Institute of Technology,Electronics Engineering Department,Surat,Gujarat,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9864330/9864331/09864428.pdf?arnumber=9864428

Reference14 articles.

1. Design of Power and Area Efficient Approximate Multipliers

2. Approximate compressors for errorresilient multiplier design;yang;Proc IEEE Int Symp Defect Fault Tolerance VLSI Nanotechnol Syst (DFTS),0

3. Design of Low Power Approximate Compressor For Dadda Multiplier;sudha;IJARECE,2015

4. Multipliers With Approximate 4–2 Compressors and Error Recovery Modules

5. Design of Approximate Compressors for Multiplication

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation of 8-bit Dadda Multiplier by Using 4:2 Compressors and Brentkung Adder for Reducing Propagation Delay in Comparison with Kogge Stone Adder;2024 Ninth International Conference on Science Technology Engineering and Mathematics (ICONSTEM);2024-04-04

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