High throughput FPGA implementation of Min-Sum LDPC Decoder Architecture for Wireless Communication Standards
Author:
Affiliation:
1. Ryazan State Radio Engineering University, RSREU,Department of Telecommunications and foundations of radio engineering,Ryazan,Russia
Funder
Russian Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9790074/9790739/09790744.pdf?arnumber=9790744
Reference12 articles.
1. IEEE Standard for Information technology-- Local and metropolitan area networks-- Specific requirements-- Part 11: Wireless LAN Medium Access Control (MAC)and Physical Layer (PHY) Specifications Amendment 5: Enhancements for Higher Throughput
2. On the design of low-density parity check codes within 0.0045 dB of the Shannon limit;chung;IEEE Commun Lett,2001
3. High-throughput layered decoder implementation for quasi-cyclic LDPC codes
4. 38.212 version 15.2.0 Release 15-3GPP Standard 5G; NR;Multiplexing and Channel Coding,2018
5. Density evolution for two improved BP-Based decoding algorithms of LDPC codes
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Improved 5G NR LDPC Decoding Algorithm Based On Box-Plus Operation;2022 IEEE/CIC International Conference on Communications in China (ICCC);2022-08-11
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