16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking-Reference-Cited by-同舟云学术

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16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking

Published:2024-02-18 Issue: Volume: Page:302-304
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Kudva Sudhir Shrikantha¹,Sinangil Mahmut Ersin¹,Tell Stephen²,Nedovic Nikola¹,Song Sanquan¹,Zimmer Brian¹,Gray C. Thomas²

Affiliation:

1. Nvidia,Santa Clara,CA

2. Nvidia,Durham,NC

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454365.pdf?arnumber=10454365

Reference6 articles.

1. A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication

2. 8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability

3. A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization

4. An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability

5. ASCH-PUF: A “Zero” Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization

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