High Throughput FPGA Implementation of LDPC Decoder Architecture for DVB-S2X Standard
Author:
Affiliation:
1. Moscow Institute of Physics and Technology,Dolgoprudny, Moscow Region,Russia
2. Ryazan State Radio Engineering University,Ryazan,Russia,Gagarina str, 59/1
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9976491/9976498/09976733.pdf?arnumber=9976733
Reference24 articles.
1. LDPC decoder architecture for DVB-S2 and DVB-S2X standards
2. Reduced Complexity Implementation of Quasi-Cyclic LDPC Decoders by Parity-Check Matrix Reordering;su;Proceedings of IEEE 10th International Conference ASIC (ASICON),2013
3. High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards
4. LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA
5. A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
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