27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration
Author:
Funder
Technology Development
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365833.pdf?arnumber=9365833
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Methods to Improve Linearity of Signal’s Analog-to-Digital Conversion with Self-Calibration;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31
2. A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator;IEEE Journal of Solid-State Circuits;2023-12
3. A CJ-LMS hybrid calibration algorithm in SAR ADC;IEICE Electronics Express;2023-08-25
4. A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems;Applied Sciences;2023-06-12
5. Design Techniques for Energy-Efficient Analog-to-Digital Converters;IEEE Open Journal of the Solid-State Circuits Society;2023
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