9.3 A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree-Reference-Cited by-同舟云学术

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9.3 A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree

Published:2021-02-13 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Park Jeongwoo,Lee Sunwoo,Jeon Dongsuk

Funder

National Research Foundation of Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09366031.pdf?arnumber=9366031

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3. EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning;IEEE Journal of Solid-State Circuits;2024-03

4. A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality;IEEE Journal of Solid-State Circuits;2024

5. C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture;IEEE Journal of Solid-State Circuits;2024-01

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