17.1 A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During Startup-Reference-Cited by-同舟云学术

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17.1 A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During Startup

Published:2021-02-13 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Xia Ziyu,Stauth Jason

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365763.pdf?arnumber=9365763

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

2. A 5V-Input Sub-1V-Output Single-Inductor Multi-Path Hybrid Buck Converter Achieving 96.1% Peak Efficiency with 250mΩ DCR Inductor;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 12V-Input 1V-1.8V-Output 94.7%-Peak-Efficiency 685A/cm³-Current-Density Hybrid DC-DC Converter with a Charge Converging Phase;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A High-Power-Density Quasi-Resonant Switched-Capacitor DC–DC Converter With Single Semiperiod Tank Current Modulation;IEEE Transactions on Power Electronics;2024-02

5. A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed V_CF Calibration and Smooth Mode Transition;IEEE Journal of Solid-State Circuits;2023-12

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