A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems

Author:

Zhu Yihong1,Zhu Wenping1,Zhu Min2,Li Chongyang1,Deng Chenchen1,Chen Chen1,Yin Shuying1,Yin Shouyi1,Wei Shaojun1,Liu Leibo1

Affiliation:

1. Tsinghua University,Beijing,China

2. Micro Innovation Integrated Circuit Design,Wuxi,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Reference8 articles.

1. Circuit Challenges from Cryptography;verbauvhede;ISSCC,2015

2. LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS

3. Cortex-M4 optimizations for {R,M} LWE schemes

4. Post-Quantum Cryptography Standardization;NIST PQC Round,2020

5. High-Apeed ECC processor Over NIST Prime Fields Applied with Toom-Cook Multiplication;ding;IEEE TCAS-I,2018

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1. High-Performance Hardware Implementation of the Saber Key Encapsulation Protocol;Electronics;2024-02-06

2. Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14

3. A 22-nm 1,287-MOPS/W Structured Data-Path Array for Binary Ring-LWE PQC;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

4. A Survey of Post-Quantum Cryptography: Start of a New Race;Cryptography;2023-08-14

5. High-speed SABER key encapsulation mechanism in 65nm CMOS;Journal of Cryptographic Engineering;2023-03-29

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