Simulation Improvements, Challenges & Solutions While Using DTL, Signal Access & DebuggerDB Optimization, PC, TC, Save-Restore-Reference-Cited by-同舟云学术

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Simulation Improvements, Challenges & Solutions While Using DTL, Signal Access & DebuggerDB Optimization, PC, TC, Save-Restore

Published:2023-11-01 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)
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Author:

Saluja Sourabh¹,Vempali Yaswani Priyanka¹,Hussain Samnani Syed Kamil¹,Manzella Joe²,Mangat Harbaksh³,Dubey Vineet Kumar⁴,Gounder Prabahar Krishna⁵,Gopani Ankit⁶

Affiliation:

1. Intel Corporation,Network & Edge Group,Bengaluru,India

2. Network & Edge Group,Allentown,US

3. Product Enablement Solutions Group,Oregon,US

4. Intel Corporation,Product Enablement Solutions Group,Bengaluru,India

5. Product Enablement Solutions Group,Arizona,US

6. Network & Edge Group,California,US

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347563/10348175/10348253.pdf?arnumber=10348253

Reference16 articles.

1. Writing Testbenches: Functional Verification of HDL Models

2. Challenges and Trends in Modern SoC Design Verification

3. Challenges in System on Chip Verification

4. Case study: Re-visiting SoC verification challenges and best practices

5. Metric- Driven Design Verification

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