A novel 0.15 μm CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions-Reference-Cited by-同舟云学术

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A novel 0.15 μm CMOS technology using W/WNx/polysilicon gate electrode and Ti silicided source/drain diffusions

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Container-title:International Electron Devices Meeting. Technical Digest
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Author:

Takagi M.T.,Miyashita K.,Koyama H.,Nakajima K.,Miyano K.,Akasaka Y.,Hiura Y.,Inaba S.,Azuma A.,Koike H.,Yoshimura H.,Suguro K.,Ishiuchi H.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/4251/12029/00553625.pdf?arnumber=553625

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effect of gate hard mask and sidewall spacer structures on the gate oxide reliability of W∕WN[sub x]∕poly-Si gate MOSFET for high density DRAM applications;Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures;2005

2. Impact ofIn SituNH3Preannealing on Sub-100 nm Tungsten Polymetal Gate Electrode during the Sealing Nitride Formation;Japanese Journal of Applied Physics;2004-04-27

3. W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory;Japanese Journal of Applied Physics;2004-04-27

4. Selective Oxidation of Silicon (100) vs. Tungsten Surfaces by Steam in Hydrogen;Journal of The Electrochemical Society;2003

5. Formation mechanism of the multilayered-structure barrier of WNx/Si(100);Applied Physics Letters;2002-06-10

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