A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-μm CMOS ULSIs-Reference-Cited by-同舟云学术

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A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-μm CMOS ULSIs

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Container-title:International Electron Devices Meeting. IEDM Technical Digest
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Author:

Uchino T.,Shiba T.,Ohnishi K.,Miyauchi A.,Nakata M.,Inoue Y.,Suzuki T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/5237/14153/00650428.pdf?arnumber=650428

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Influence of Design and Process Parameters of 32-nm Advanced-Process High-k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects;Journal of Electronic Materials;2017-05-22

2. Low thermal budget for Si and SiGe surface preparation for FD-SOI technology;Applied Surface Science;2016-05

3. The revolution in SiGe: impact on device electronics;Applied Surface Science;2004-03

4. Isotropic/anisotropic growth behavior and faceting morphology of Si epitaxial layer selectively grown by cold wall ultrahigh vacuum chemical vapor deposition;Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures;2004

5. Metal Silicides in CMOS Technology: Past, Present, and Future Trends;Critical Reviews in Solid State and Materials Sciences;2003-11

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