Sub 50-nm FinFET: PMOS-Reference-Cited by-同舟云学术

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Sub 50-nm FinFET: PMOS

Published: Issue: Volume: Page:
ISSN:
Container-title:International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)
language:
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Author:

Xuejue Huang ,Wen-Chin Lee ,Charles Kuo ,Hisamoto D.,Leland Chang ,Kedzierski J.,Anderson E.,Takeuchi H.,Yang-Kyu Choi ,Asano K.,Subramanian V.,Tsu-Jae King ,Bokor J.,Chenming Hu

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6669/17838/00823848.pdf?arnumber=823848

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1. A novel method to solve analytically the non-linear Poisson equation in the inversion layer of a MOSFET;Semiconductor Science and Technology;2024-08-13

2. High-density vertical sidewall MoS2 transistors through T-shape vertical lamination;Nature Communications;2024-07-10

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4. Comparison of Total Ionizing Dose Effects in 16-nm Core and I/O n-FinFETs;IEEE Transactions on Nuclear Science;2024-02

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