A 7.9/5.5 psec room/low temperature SOI CMOS-Reference-Cited by-同舟云学术

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A 7.9/5.5 psec room/low temperature SOI CMOS

Published: Issue: Volume: Page:
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Container-title:International Electron Devices Meeting. IEDM Technical Digest
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Author:

Assaderaghi F.,Rausch W.,Ajmera A.,Leobandung E.,Schepis D.,Wagner L.,Wann H.-J.,Bolam R.,Yee D.,Davari B.,Shahidi G.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx3/5237/14153/00650413.pdf?arnumber=650413

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits;International Journal of Electronics;2003-10

2. Frontiers of silicon-on-insulator;Journal of Applied Physics;2003-05

3. Silicon on Insulator;Advanced Semiconductor and Organic Nano-Techniques;2003

4. Performance analysis of tapered gate in PD/SOI CMOS technology;International Journal of Electronics;2002-04

5. Thermal effect of 0.1 μm partially depleted SOI CMOSFET;Microelectronic Engineering;2001-11

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