Characteristics and applications of a 0.6 μm bipolar-CMOS-DMOS technology combining VLSI non-volatile memories
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx3/4251/12029/00553627.pdf?arnumber=553627
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Non Volatile Memory in Advanced Smart Power technology: product requirements and integration solutions;2022 IEEE International Memory Workshop (IMW);2022-05
2. 80–100 V Low-Side Lateral Double-Diffused Metal Oxide Semiconductor Device with Sided Isolation of 0.35 um CMOS-Compatible Process;Sensors and Materials;2017
3. Design of 256 bit single-poly MTP memory based on BCD process;Journal of Central South University;2012-12
4. High-Side nLDMOS Design for Ensuring Breakdown Voltages Over 100 V;Journal of Nanoscience and Nanotechnology;2011-07-01
5. Pad Over Active (POA) solutions for three metal level BCD5 mixed power process - Design and validation of ESD protections;Microelectronics Reliability;2003-09
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