Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node-Reference-Cited by-同舟云学术

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Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node

Published:2021-10-06 Issue: Volume: Page:
ISSN:
Container-title:2021 International Semiconductor Conference (CAS)
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Author:

Sudarsanan Akhil,Badami Oves,Nayak Kaushik

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9604113/9604114/09604183.pdf?arnumber=9604183

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level;Microelectronics Reliability;2024-09

2. Study of gate current in advanced MOS architectures;Solid-State Electronics;2022-08

3. Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications;Silicon;2022-03-03

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