Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections
Author:
Affiliation:
1. UMR 6285, Lab-STICC, Univ. Bretagne-Sud,Lorient,France
2. Inria, Univ. Rennes, CNRS, IRISA,France
3. UMR 6285, Lab-STICC, ENSTA Bretagne,Brest,France
4. CentraleSupélec, Inria, CNRS, IRISA, Univ,Rennes,France
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10190553/10190632/10190700.pdf?arnumber=10190700
Reference16 articles.
1. ScatterCache: Thwarting cache attacks via cache set randomization;werner;Proc 28th USENIX Security Symposium (USENIX Security),2019
2. New cache designs for thwarting software cache-based side channel attacks
3. FLUSH+RELOAD: A high resolution, low noise, l3 cache side-channel attack;yarom;Proc 23th USENIX Security Symposium (USENIX Security),2014
4. Compiler-Assisted Hardening of Embedded Software Against Interrupt Latency Side-Channel Attacks
5. CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping
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