In-Memory Half Adder Computation using CNTFET Transistors in 8T SRAM
Author:
Affiliation:
1. Motilal Nehru National Institute of Technology Allahabad,Department of Electronics and Communication Engineering,Prayagraj,India
2. Rajiv Gandhi Institute of Petroleum Technology,Department of Electrical and Electronics Engineering,Jais,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10110034/10110036/10110189.pdf?arnumber=10110189
Reference17 articles.
1. Design and analysis of different types SRAM cell topologies
2. A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part II: Extrinsic Elements and Performance Assessment;lee,0
3. CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays
4. XOR-CIM
5. A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime—Part I: Intrinsic Elements;lee,0
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