Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design-Reference-Cited by-同舟云学术

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Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design

Published:2017-07 Issue:7 Volume:36 Page:1181-1192
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhang Yaojun^ORCID,Yan Bonan,Wang Xiaobin,Chen Yiran

Funder

Division of Electrical Communications and Cyber Systems

Division of Computer and Network Systems

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/7951135/07600421.pdf?arnumber=7600421

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. DCR: Deterministic Crash Recovery for NAND Flash Storage Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-12

2. A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-07

3. Recent Technology Advances of Emerging Memories;IEEE Design & Test;2017-06

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