Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation-Reference-Cited by-同舟云学术

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation

Published:2019-07 Issue:7 Volume:38 Page:1359-1372
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Herdt Vladimir^ORCID,Le Hoang M.^ORCID,Grobe Daniel^ORCID,Drechsler Rolf^ORCID

Funder

German Federal Ministry of Education and Research through the Project CONFIRM

Bundesministerium für Bildung und Forschung

German Research Foundation through the Reinhart Koselleck Project

University of Bremen’s Graduate School SyDe

German Excellence Initiative

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

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