Robust Chip-Level Clock Tree Synthesis-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

Robust Chip-Level Clock Tree Synthesis

Published:2011-06 Issue:6 Volume:30 Page:877-890
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Rajaram Anand,Pan David Z.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5768121/05768141.pdf?arnumber=5768141

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

3. Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

4. Timing ECO Approach Addressing Clock Gating Cells for Anti-Aging Purposes to Save Runtime;2023 International Conference on Electrical, Computer and Energy Technologies (ICECET);2023-11-16

5. A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号京ICP备18003416号-3